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AD7710 Signal Conditioning ADC Datasheet
Photograph
Features
Charge Balancing ADC
- - 24 Bits No Missing Codes
- - ±0.0015% Nonlinearity
Two-Channel Programmable Gain Front End
- - Gains from 1 to 128
- - Differential Inputs
Low-Pass Filter with Programmable Filter Cutoffs
Ability to Read/Write Calibration Coefficients
Bidirectional Microcontroller Serial Interface
Internal/External Reference Option
Single or Dual Supply Operation
Low Power (25mW typ) with Power-Down Mode (7mW typ)
Pin Layout
Pin Description
Pin Number | Description |
---|---|
1 | SCLK - Serial Clock |
2 | MCLK IN - Master Clock In |
3 | MCLK OUT - Master Clock Out |
4 | A0 - Address Input |
5 | SYNC - Synchronization (Active Low) |
6 | MODE - Logic Input |
7 | +AIN1 - Analog Input Channel 1 |
8 | -AIN1 - Analog Input Channel 1 |
9 | +AIN2 - Analog Input Channel 2 |
10 | -AIN2 - Analog Input Channel 2 |
11 | Vss - Analog Negative Supply |
12 | AVdd - Analog Positive Supply |
13 | Vbias - Input Bias Voltage |
14 | REF IN- - Reference Input |
15 | REF IN+ - Reference Input |
16 | REF OUT - Reference Output |
17 | Iout - Compensation Current Output |
18 | AGND - Analog Ground |
19 | TFS - Transmit Frame Synchronization (Active Low) |
20 | RFS - Receive Frame Synchronization (Active Low) |
21 | DRDY - Logic Output (Active Low) |
22 | SDATA - Serial Data |
23 | DVdd - Digital Positive Supply |
24 | DGND - Digital Ground |
Dimensional Drawing
Technical Data