ATMega103 64-Pin 4MHz 128kB AVR Microcontroller Technical Data

Photograph

Features

Utilizes the AVR RISC Architecture
High-performance and Low-power 8-bit RISC Architecture
- - 121 Instructions - Most Single Clock Cycle Execution
- - 32 x 8 General Purpose Working Registers
- - Up to 6 MIPS Throughput at 6MHz
- - Fully Static Operation
Data and Nonvolatile Program Memory
- - 128k Bytes of In-System Self-Programmable Flash
- - Programmable Lock for Flash Program and EEPROM Data Security
- - 4K Bytes EEPROM
- - 4K Bytes Internal SRAM
- - SPI Interface for In-System Programming
Peripheral Features
- - On-chip Analog Comparator
- - Programmable Watchdog Timer with Separate On-chip Oscillator
- - Real Time Counter with Separate Oscillator
- - Master/Slave SPI Serial Interface
- - Two 8-bit Timer/Counters with Separate Prescalar, Compare
- - Expanded 16-bit Timer/Counter with Separate Prescaler, Compare and Capture mode
- - 8-channel, 10-bit ADC
Special Microcontroller Features
- - Low-power Idle, Power-save and Power-down Modes
- - Software Selectable Clock Frequency
- - External and Internal Interrupt Sources
I/O and Packages
- - 32 Programmable I/O Lines
- - 64-lead TQFP

Pin Layout

Pin Description

Pin Number	Description
1	PEN - Programming Enable
2 - 9	PE0 - PE7 - Port E
10 - 17	PB0 - PB7 - Port B
18	TOSC2 - Oscillator Output
19	TOSC1 - Oscillator Input
20	RESET - Reset
21	Vcc - Positive Power Supply
22	GND - Ground
23	XTAL2 - Crystal
24	XTAL1 - Crystal
25 - 32	PD0 - PD7 - Port D
33	WR - External SRAM Write Strobe
34	RD - External SRAM Read Strobe
35 - 42	PC0 - PC7 - Port C
43	ALE - Address Latch Enable
44 - 51	PA7 - PA0 - Port A
52	Vcc - Positive Power Supply
53	GND - Ground
54 - 61	PF7 - PF0 - Port F
62	AREF - Analog Reference
63	GND - Ground
64	AVCC - Analog Power Supply

Dimensional Drawing

Technical Data

Datasheet

Microchip Web Site - Datasheet for ATmega103L

Application Notes