dsPIC30F2010 28-pin 16-bit Digital Signal Controller Datasheet

High-Performance RISC CPU

• - Modified Harward Architecture
• - C Compiler Optimized Instruction Set Architecture
• - DC - 40 MHz osc./clock input
• - 24-bit wide instructions, 16-bit wide data path
• - Eight User Selectable Priority Levels for Each Interrupt
• - 17-bit x 17-bit Single Cycle Hardware Multiplier
• - 12 kBytes Flash Program Memory
• - 512 Byte RAM Data Memory
• - 1024 Byte EEPROM Data Memory

Peripheral Features

• - High current sink/source 25mA/25mA
• - Three 16-bit timer/counters
• - Four 16-bit Capture Input Functions
• - Two 16-bit Compare/PWM Output Functions
• - 3-wire SPI (supports all 4 SPI modes)
• - I²C Master and Slave mode
• - Addressable USART Module
• - Six Channel 10-bit Analog-to-Digital Converter

Motor Control PWM Features

• - Six PWM Output Channels
• - Four Duty Cycle Generators
• - Dedicated Time Base with Four Modes
• - Programmable Output Polarity
• - Dead-Time Control for Complementary Mode
• - Manual Output Control
• - Trigger for Synchronized A/D Conversions

Quadrature Encoder Interface Module Features

• - Phase A, Phase B and Index Pulse Input
• - 16-bit Up/Down Position Counter
• - Count Direction Status
• - Position Measurement (x2 and x4) Mode
• - Programmable Digital Noise Filter on Inputs
• - Alternate 16-bit Timer/Counter Mode
• - Interrupt on Position Counter Rollover/Underflow

Special Microcontroller Features

• - Power-On Reset
• - Power-up Timer (PWRT) and Oscillator Start-Up Timer (OST)
• - 1,000 erase/write cycles Enhanced Flash Program Memory
• - 1,000,000 typical erase/write cycles EEPROM Data Memory
• - Programmable Code Protection
• - Power Saving SLEEP mode

CMOS Technology

• - Low power, high speed CMOS FLASH technology
• - Fully Static Design
• - Wide Operating Voltage Range (2.0V to 5.5V)

I/O and Packages

• - 20 I/O pins with individual direction control
• - 28-pin DIP