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New Improved Data Chipset for Internet Delivery over the Wireless Network

National Semiconductor improves Intenet delivery over the Wireless Network

National Semiconductor has announced a new flexible 10:1 serializer/deserializer for telecom and datacom systems. The chipset lowers overall system cost by simplifying the movement of bits around the digital infrastructure found in base stations for 3G mobile phones and internet access appliances. National's devices use LVDS-based technology to achieve system economies by driving the trend to high-speed data transfer over a single differential wiring pair. With this chipset, National Semiconductor has further expanded its product portfolio for delivering high-bandwidth digital data through the equipment in the Internet and wireless communications infrastructure.

National Semiconductor "As chip performance goes up and the price of Mbps goes down, printed circuit boards, cables, and connectors do not follow Moore's Law and, therefore, inhibit system cost reduction," said Stephen Kempainen, product marketing manager for National's Interface Group. "Base stations for EDGE (Enhanced Data Rates for Global Evolution) and 3G cellular systems require hundreds of Mbps data throughput to accommodate wireless Internet data, voice, and video streams. Because data transmission rates are now an order of magnitude greater than before, communication system designers must have this serializer and deserializer chipset's efficient throughput. They can apply National Bus LVDS technology to speed integrated data, voice, and video traffic through the infrastructure at a considerable savings in system cost."

By serializing data and embedding the clock in the data stream, the chipset allows a reduction of printed circuit board area, while minimizing cable and connector width. Low power dissipation, elimination of the termination power supply, and reduction of cooling system requirements also lower system cost.

The Bus LVDS-based DS92LV1023 serializes 10-bit parallel bus data to a single serial-stream data path at rates between 400 to 660 Mbps. The DS92LV1224 deserializer accepts the serial stream, recovers the clock and data, and delivers both to the receiver parallel interface.

The DS92LV1023 serializer input accepts as many as 10 parallel bits with the associated transmit clock to latch the parallel bits into the device It then serializes the data and embeds the clock for serial transport, eliminating the chance of clock and data skew. The chipset allows users to send data either point-to-point, or to bus data to multiple deserializers and provides the bandwidth necessary to transfer digital data from the RF converter to DSP baseband processing units. Moreover, the DS92LV1023 is the only serializer with LVDS capability and a transmitter that can drive up to a 20-slot backplane.

CMOS technology not only gives the DS92LV1023 and DS92LV1224 the lowest power consumption of any serial data rate device on the market, but also provides other cost and system benefits. Power-saving CMOS translates to less heat dissipation than competing devices manufactured using BiCMOS or gallium arsenide processes. Less thermal management means reduced system complexity.

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[Reprinted with kind permission from National Semiconductor]

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