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First RISC-based Programmable System-On-A-Chip Announced
Better Performance and Lower Power Consumption for these new AVR Microcontrollers
Atmel Corporation has announced that it has begun shipments of the industry's first
RISC Processor-based FPSLIC (Field Programmable System Level Integration
Circuit) to customers in the United States and Europe. FPSLIC devices are
rated at 30 MIPS at 40 MHz operation and consume a fraction of the power
of conventional FPGA devices. FPSLIC is ideal for low power and portable
applications including telecommunications, networking, instrumentation and
automotive. Today FPSLIC can increase speed, reduce size and lower power
consumption in systems requiring an 8-bit microcontroller and up to 50,000
gates of programmable logic (FPGA or PLD).
FPSLIC devices combine Atmel's embedded AT40K FPGA core with a high
performance version of the popular AVR 8-bit RISC Microcontroller, 2
UARTs, Timer/Counters, Interrupt Controller, Programmable I/O Ports and
36K bytes of Program and Data SRAM on a single chip. Additional
peripherals and custom logic can be programmed in the FPGA. The benefits
of this solution include 70% area reduction, 50% lower power consumption,
50% performance improvement, and significantly faster time-to-market than
discrete and other programmable solutions. The microcode for the AVR
microcontroller and the FPGA logic can be reconfigured an unlimited number
of times, making FPSLIC devices an ideal platform for developing multiple
end products based on a single integrated solution.
"There are 2 emerging programmable technologies available to implement
system-on-chip designs," according to Joel Rosenberg, Atmel's Product Line
Director for Programmable SLI products. The first involves implementing
the design in a traditional high density FPGA, while the second is
implemented in a programmable system chip, such as FPSLIC. A single FPSLIC
device is made up of embedded system blocks including processor,
peripherals, memory, programmable logic and other intellectual property
cores.
"The economics of system design - including unit cost, speed, power
consumption, design tools, time-to- market, risk and availability make
FPSLIC the technology of choice over FPGA for implementing system-on- chip
designs. It simply doesn't make sense to delay product development and
increase design risk by utilizing expensive, scarce engineering resources
to recompile an already proven processor core in a more expensive, less
efficient FPGA. The cost of a million gate equivalent FPGA today is more
than $250 in high volume; while the cost of a faster, lower power, more
efficient FPSLIC device is under $50 today. With Atmel's co-verification
tools, design time can be reduced by several months by allowing both
hardware and software development and verification to be performed early
in the design cycle, eliminating costly design changes and production
delays." Rosenberg concluded.
"Like their custom gate array and ASIC predecessors in the 1980s and
1990s, custom system-on-chip capability is extremely expensive and out of
reach for most design projects today," according to Martin Mason,
Programmable SLI Marketing Manager for Atmel. "Design tools, including
co-verification, can cost in excess of $100K per seat; intellectual
property cores are expensive and largely unproven, the mask charges for a
gate array are in excess of $200K, and the system level knowledge and
experience required to successfully implement a SOC is not readily
available. Unless a company will ship millions of systems utilizing the
custom system-on-chip, it is hard to justify the cost, risk and
time-to-market issues associated with custom SOC development today.
"Now every designer can benefit from the combination of system-level
integration and programmability in a single device -- at a price level
that supports volume production. In addition, the Atmel software/hardware
design environment is the first programmable solution to include
co-verification, a design methodology that enables designers to evaluate
hardware/software tradeoffs early in the design process, resulting in
faster, more efficient lower power designs while reducing design time by
1-3 months. Until now co-verification has been used primarily for embedded
processors implemented in ASIC designs requiring much more expensive
development tools." Mason continued.
"Shipping our first FPSLIC products today is a significant milestone in
bringing System Level Integration to the desktops of designers everywhere.
While other PLD and FPGA vendors are just realizing the potential of this
enormous market, Atmel has already addressed the SOC issues and is
shipping products today. Atmel has designed and manufactured ASICs
(application specific integrated circuits) with embedded AVR, ARM, DSPs
and other processor cores for many years now. The FPSLIC architecture is
fully scalable and takes full advantage of Atmel's advanced ASIC and FPGA
experience and capabilities. In addition our design tools are modular,
providing the ability to support most industry standard 8-, 16-, 32- and
64-bit processors available today." Mason concluded.
The company's Web site address is http://www.atmel.com/.
[Reprinted with kind permission from Atmel Corporation]
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